Morteza Gholipour Articles List

List of Articles Morteza Gholipour

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1 - Analysis and Evaluation of the Effect of Design Parameters on Timing Parameters and Power Consumption of Static Flip-Flop in 16 nm Technology Node
E. Mahmoodi Morteza Gholipour
20.1001.1.16823745.1398.17.2.14.9

Flip-flop is one of the important elements in the digital circuit’s design, which its performance affects the speed and power of the system. In this paper, appropriate simulations are used to obtain the timing parameters of the static flip-flop and investigate the effec More

Flip-flop is one of the important elements in the digital circuit’s design, which its performance affects the speed and power of the system. In this paper, appropriate simulations are used to obtain the timing parameters of the static flip-flop and investigate the effect of the width of different transistors on these parameters. Then, the effects of the supply voltage and manufacturing process parameters variation on the performance of the flip-flop are investigated. The widths of transistors are determined based on the desired energy-delay product (EDP) and power-delay product (PDP) for these two cases separately. Then, the effect of voltage variations on the increase of EDP and PDP are investigated compared to the base flip-flop. We used a static D-type flip-flop in our simulations. The simulations were performed using the HSPICE in 16 nm technology node at 1 GHz frequency. Manuscript profile
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2 - Evaluating Schottky-Barrier-Type GNRFETs-Based Static Flip-Flop Characteristic under Manufacturing Process Parameters Variations
Erfan Abbasian Morteza Gholipour
20.1001.1.16823745.1399.18.2.14.6

Graphene nanoribbon field-effect transistors (GNRFETs) have emerged as encouraging replacement candidate for traditional silicon-based transistor in next-generation technology. Since GNRFETs’ channel is about a few nanometers, impact of manufacturing process variations More

Graphene nanoribbon field-effect transistors (GNRFETs) have emerged as encouraging replacement candidate for traditional silicon-based transistor in next-generation technology. Since GNRFETs’ channel is about a few nanometers, impact of manufacturing process variations on circuits’ performance is very large. In this paper, impact of manufacturing process variations such as oxide thickness, channel length, and number of dimer lines on schottky-barrier-type GNRFETs (SB-GNRFETs)-based static flip-flop characteristics such as delay, power, and energy-delay-product (EDP) is evaluated and analyzed. Furthermore, Monte-Carlo (MC) simulations have been performed for statistical analysis of these variations. With change in the oxide thickness from its nominal value to 1.15 nm, the propagation delay and EDP are increased by 31.57% and 60.62%, respectively. Also, the channel length variation has the least effect on flip-flop characteristic. The propagation delay and EDP are increased by 315.48 % and 204.79%, respectively, when the number of dimer lines increases by one from its nominal value. The results obtained from MC simulations show that the oxide thickness variations lead to spread of 2.46, 1.57 and 2.39 times higher than the number of dimer lines variations in histogram distribution of flip-flop characteristic. Manuscript profile
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3 - Improving On-Off Current Ratio (Ion/Ioff) in Schottky-Barrier-Type Graphene Nanoribbon FETs
Morteza Gholipour
20.1001.1.16823745.1400.19.1.3.0

Schottky-barrier-type graphene nanoribbon transistors (SB-GNRFET), despite their prominent characteristics compared to conventional transistors, have a relatively high off-current and a low Ion/Ioff ratio. In this paper, a new structure of SB-GNRFET is presented in whic More

Schottky-barrier-type graphene nanoribbon transistors (SB-GNRFET), despite their prominent characteristics compared to conventional transistors, have a relatively high off-current and a low Ion/Ioff ratio. In this paper, a new structure of SB-GNRFET is presented in which the gate of the transistor is divided into two parts. A constant voltage is connected to the gate located on the drain side, and the gate located on the source side is the main gate of the transistor. The proposed SB-GNRFET is simulated using non-equilibrium Green functions-based numerical simulator under different geometric and physical characteristics and in biases. The simulation results show Ion/Ioff ratio improvement of up to 6.7-fold at VDS = 0.8 V. At this voltage the ratio has increased from 1.2 in the normal SB-GNRFET transistor to 8.01 in the new transistor and the off current has been reduced from 5 µA to 0.7 µA. Also at VDS = 0.6 V, as the supply voltage, the Ion/Ioff ratio increased from 3.97 to 15.8 and the off current decreased from 0.63 µA to 0.16 µA. Manuscript profile
Open Access Article
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4 - Performance Evaluation of TMDFET-based SRAM Memory Cell Compared to Si-MOSFET Technology
فرزانه ایزدی نسب Morteza Gholipour
20.1001.1.16823745.1400.19.3.13.4

Transition metal dichalcogenides FETs (TMDFETs) are among the emerging devices that have been considered by researchers in recent years. In this paper, the effect of parameter variations, temperature and power supply on the performance of TMDFET transistors has been inv More

Transition metal dichalcogenides FETs (TMDFETs) are among the emerging devices that have been considered by researchers in recent years. In this paper, the effect of parameter variations, temperature and power supply on the performance of TMDFET transistors has been investigated in comparison with Si-MOSFET technology. The results indicate that TMDFET is less sensitive to these variations compared to Si-MOSFET devices. By selecting the appropriate transistors size ratios, the performance of the TMDFET-based conventional 6-transistor static random access memory cell is evaluated in comparison with the Si-MOSFET in 16nm technology. Simulations are performed at room temperature, 0.7 V supply voltage and the same conditions for both TMDFET and Si-MOSFET devices. The results of the simulations show that TMDFET-based SRAM cell has 29.44% more WTP, corresponding to more writing ability, 49.49% more WTI×WTV, corresponding to higher writing noise margin, and 29.48% lower read delay. In other words, a TMDFET-based SRAM cell performs better than Si-MOS-SRAM in terms of write ability, static read margin, and read delay. Manuscript profile

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List of Articles Morteza Gholipour