Performance Evaluation of TMDFET-based SRAM Memory Cell Compared to Si-MOSFET Technology
Subject Areas : electrical and computer engineering
فرزانه
ایزدی نسب
1
Morteza
Gholipour
2
(Babol Noshirvani University of Technology)
Keywords: 6T-SRAM, static random access memory, transition metal dichalcogenides FET (TMDFET), process, voltage and temperature variations (PVT),
Abstract :
Transition metal dichalcogenides FETs (TMDFETs) are among the emerging devices that have been considered by researchers in recent years. In this paper, the effect of parameter variations, temperature and power supply on the performance of TMDFET transistors has been investigated in comparison with Si-MOSFET technology. The results indicate that TMDFET is less sensitive to these variations compared to Si-MOSFET devices. By selecting the appropriate transistors size ratios, the performance of the TMDFET-based conventional 6-transistor static random access memory cell is evaluated in comparison with the Si-MOSFET in 16nm technology. Simulations are performed at room temperature, 0.7 V supply voltage and the same conditions for both TMDFET and Si-MOSFET devices. The results of the simulations show that TMDFET-based SRAM cell has 29.44% more WTP, corresponding to more writing ability, 49.49% more WTI×WTV, corresponding to higher writing noise margin, and 29.48% lower read delay. In other words, a TMDFET-based SRAM cell performs better than Si-MOS-SRAM in terms of write ability, static read margin, and read delay.
[1] J. D. Plummer and B. P. Griffin, "Material and process limits in silicon VLSI technology," Proceedings of the IEEE, vol. 89, no. 3, pp. 240-258, Mar. 2001.
[2] A. A. Kumar and C. Anu, "Performance analysis of 6T SRAM cell on planar and FinFET technology," in Proc. IEEE Int. Conf. on Communication and Signal Processing, ICCSP'19, pp. 0375-0379, Chennai, India, 4-6 Apr. 2019.
[3] P. K. Patel, M. M. Malik, and T. K. Gupta, "Performance evaluation of single-ended disturb-free CNTFET-based multi-Vt SRAM," Microelectronics J., vol. 90, pp. 19-28, Jun. 2019.
[4] E. Abbasian and M. Gholipour, "A variation-aware design for storage cells using Schottky-barrier-type GNRFETs," J. of Computational Electronics, vol. 19, no. 3, pp. 987-1001, 2020.
[5] C. H. Yu, P. Su, and C. T. Chuang, "Impact of random variations on cell stability and write-ability of low-voltage SRAMs using monolayer and bilayer transition metal dichalcogenide (TMD) MOSFETs," IEEE Electron Device Letters, vol. 37, no. 7, pp. 928-931, Jul. 2016.
[6] C. H. Yu, P. Su, and C. T. Chuang, "Performance and stability benchmarking of monolithic 3-D logic circuits and SRAM cells with monolayer and few-layer transition metal dichalcogenide MOSFETs," IEEE Trans. on Electron Devices, vol. 64, no. 5, pp. 2445-2451, May 2017.
[7] M. Gholipour, Y. Y. Chen, and D. Chen, "Compact modeling to device-and circuit-level evaluation of flexible TMD field-effect transistors," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 4, pp. 820-831, Apr. 2017.
[8] A. J. Wilson and A. D. Yoffe, "The transition metal dichalcogenides discussion and interpretation of the observed optical, electrical and structural properties," Advances in Physics, vol. 18, no. 73, pp. 193-335, 1969.
[9] K. S. Novoselov, et al., "Two-dimensional atomic crystals," Proc. of the National Academy of Sciences, vol. 102, no. 30, pp. 10451-10453, 2005.
[10] A. Ayari, E. Cobas, O. Ogundadegbe, and M. S. Fuhrer, "Realization and electrical characterization of ultrathin crystals of layered transition-metal dichalcogenides," J. of Applied Physics, vol. 101, no. 1, Article No.: 014507, 2007.
[11] H. S. S. Ramakrishna Matte, et al., "MoS2 and WS2 analogues of graphene," Angewandte Chemie International Edition, vol. 49, no. 24, pp. 4059-4062, Jun. 2010.
[12] B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti, and A. Kis, "Single-layer MoS 2 transistors," Nature Nanotechnology, vol. 6, no. 3, pp. 147-150, 2011.