The performance of Networks-on-Chip is highly dependent to the incorporated routing algorithms. In recent years, many routing algorithms have been proposed for 2D and 3D Networks-on-Chip. In 3D integrated circuits, different devices are stacked through silicon via in wh More
The performance of Networks-on-Chip is highly dependent to the incorporated routing algorithms. In recent years, many routing algorithms have been proposed for 2D and 3D Networks-on-Chip. In 3D integrated circuits, different devices are stacked through silicon via in which the vertical connections are vulnerable to manufacturing process variations. Therefore, because of the high impact of faulty links or nodes on the performance of a Network-on-Chip, utilizing a fault-tolerant routing algorithm is of great importance especially for 3D Networks-on-Chip in which the vertical links are more vulnerable. In this paper, a new fault-tolerant routing algorithm called FT-ZXY is proposed to be used in 3D Networks-on-Chip. This routing method is capable of tolerating multiple vertical faulty links in addition to single horizontal faulty links without using any virtual channels thus incurs a very low hardware overhead. Experimental results reveal that the proposed routing algorithm has more reliability compared to the previous designs while incurs less latency and requires lower area and power overheads.
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