Mojtaba Valinataj Articles List

List of Articles Mojtaba Valinataj

Open Access Article
- Abstract Page
- Full-Text
1 - A Fault-Tolerant Routing Algorithm for 3D Networks-on-Chip
M. Taghizadeh Firoozjaee M. Taghizadeh Firoozjaee M. Taghizadeh Firoozjaee
20.1001.1.16823745.1395.14.2.18.2

The performance of Networks-on-Chip is highly dependent to the incorporated routing algorithms. In recent years, many routing algorithms have been proposed for 2D and 3D Networks-on-Chip. In 3D integrated circuits, different devices are stacked through silicon via in wh More

The performance of Networks-on-Chip is highly dependent to the incorporated routing algorithms. In recent years, many routing algorithms have been proposed for 2D and 3D Networks-on-Chip. In 3D integrated circuits, different devices are stacked through silicon via in which the vertical connections are vulnerable to manufacturing process variations. Therefore, because of the high impact of faulty links or nodes on the performance of a Network-on-Chip, utilizing a fault-tolerant routing algorithm is of great importance especially for 3D Networks-on-Chip in which the vertical links are more vulnerable. In this paper, a new fault-tolerant routing algorithm called FT-ZXY is proposed to be used in 3D Networks-on-Chip. This routing method is capable of tolerating multiple vertical faulty links in addition to single horizontal faulty links without using any virtual channels thus incurs a very low hardware overhead. Experimental results reveal that the proposed routing algorithm has more reliability compared to the previous designs while incurs less latency and requires lower area and power overheads. Manuscript profile
Open Access Article
- Abstract Page
- Full-Text
2 - Design of Floating-Point Multipliers with Normal and Fault-Tolerant Operations Using Reduced-Precision Computin
M. Mohajer M. Taghizadeh Firoozjaee
20.1001.1.16823745.1397.16.2.1.9

Multiplication is one of the important computations required for different signal processing applications especially regarding voice and image. However, the multipliers as digital circuits are susceptible to different environmental effects such as noises. In this paper, More

Multiplication is one of the important computations required for different signal processing applications especially regarding voice and image. However, the multipliers as digital circuits are susceptible to different environmental effects such as noises. In this paper, a new approach is proposed for designing a 32-bit floating-point multiplier which can operate in two operational modes, normal and fault-tolerant, dependent to the environmental conditions. In the fault-tolerant mode, by reducing the normal precision and accepting a negligible error in the output, a portion of preliminary circuit is released which is used for redundant computations in order to detect or correct errors. This way, two multiplier architectures with error detection or correction capability are proposed that have a beneficial reliability against different types of permanent and transient faults. The implementation results show that in the fault-tolerant mode, maintaining 13 bits instead of 23 bits for the mantissa will be enough to achieve an error detecting multiplier, and maintaining 11 bits will be enough to achieve an error correcting multiplier with acceptable area and power overheads (from 12% to 26%) while their precisions are enough for most applications. Manuscript profile
Open Access Article
- Abstract Page
- Full-Text
3 - Enhancing Speed, Area and Power Consumption of Carry Select Adders Using a New Grouping Structure
A. Mohammad Nezhad M. Taghizadeh Firoozjaee
20.1001.1.16823745.1397.16.4.14.6

Design of low-cost and high-speed datapath is very important for current computing systems. The adders are the essential parts of datapaths in computing systems. Among different types of adders, the carry select adder (CSeA) has a high speed while having the area overhe More

Design of low-cost and high-speed datapath is very important for current computing systems. The adders are the essential parts of datapaths in computing systems. Among different types of adders, the carry select adder (CSeA) has a high speed while having the area overhead, as well. A factor influencing the speed of this adder is the incorporated grouping structure dependent to its components' delay. In this paper, at first, the delay and area of different existing CSeA architectures are reduced by utilizing a fast and small multiplexer. Then, a new grouping structure is proposed for more delay reduction based on a delay analysis. Implementation and experimental results show that applying the proposed grouping and modifications on different CSeA architectures leads to a high delay reduction in the add operation compared to the best existing grouping structure. For example, the amount of delay reduction in the investigated 32-bit CSeA architectures is more than 33%. In addition, the average reduction of power-delay-product criterion for 32-bit and 64-bit CSeAs utilizing the proposed grouping equals45% and 35%, respectively, compared to the CSeAs incorporating the current best grouping. Manuscript profile

Current Issue

Published Issues

Menu

Browse

List of Articles Mojtaba Valinataj