سرعت بالا

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1 - Design, Optimization, and Finite Element Analysis of a Disk-Type Permanent Magnet Synchronous Motor
S. A. Seyedi Seadati A. Halvaei Niasar

This paper proposes to design, optimization and finite element simulation of an axial-flux, super-high speed, permanent magnet motor. The target motor with 0.5 hp rated power at speed of 60,000 rpm is used in a special industrial application. Based on nominal specificat More

This paper proposes to design, optimization and finite element simulation of an axial-flux, super-high speed, permanent magnet motor. The target motor with 0.5 hp rated power at speed of 60,000 rpm is used in a special industrial application. Based on nominal specifications of the motor and using analytical relations of motor design, the design calculations, sizing and motor dimensions are investigated. Due to special application of the target motor that needs to the demanded torque with minimum current and copper losses, the dimensions and design specifications of motor is optimized via genetic algorithm based on a torque per ampere cost function. Optimization algorithm determines the optimum value of airgap, permanent magnet flux density, current density and turns number of stator windings. To demonstrate of analytical design and optimization results, using 3-D model of motor in Maxwell software, finite element analysis are carried out in Magneto-static and Transient modes. The FEM simulation results confirm the analytical design results. Moreover, they show the significant reduction in RMS current and copper loss at rated torque. There is a good agreement between the values of torque, motor efficiency, and flux density resulted from both methods. Manuscript profile
Open Access Article
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2 - A Step towards All-Optical Deep Neural Networks: Utilizing Nonlinear Optical Element
Aida Ebrahimi Dehghan Pour S. K.
20.1001.1.16823745.1401.20.3.2.0

In recent years, optical neural networks have received a lot of attention due to their high speed and low power consumption. However, these networks still have many limitations. One of these limitations is implementing their nonlinear layer. In this paper, the implement More

In recent years, optical neural networks have received a lot of attention due to their high speed and low power consumption. However, these networks still have many limitations. One of these limitations is implementing their nonlinear layer. In this paper, the implementation of nonlinear unit for an optical convolutional neural network is investigated, so that using this nonlinear unit, we can realize an all-optical convolutional neural network with the same accuracy as the electrical networks, while providing higher speed and lower power consumption. In this regard, first of all, different methods of implementing optical nonlinear unit are reviewed. Then, the impact of utilizing saturable absorber, as the nonlinear unit in different layers of CNN, on the network’s accuracy is investigated, and finally, a new and simple method is proposed to preserve the accuracy of the optical neural networks utilizing saturable absorber as the nonlinear activating function. Manuscript profile
Open Access Article
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3 - Design and Simulation of a Low Power and High-Speed CMOS Double-Tail Comparator
Akbar Heidaritabar habib Adarang seyed saleh Ghoreishi Reza Yousefi
20.1001.1.16823745.1402.21.1.5.6

The need for low power and high-speed ADC pushes for dynamic comparators to reduce power consumption and maximize speed. This paper presents an analysis of delay, speed, and comparator considerations, and analytical expressions are derived. Using the equation expression More

The need for low power and high-speed ADC pushes for dynamic comparators to reduce power consumption and maximize speed. This paper presents an analysis of delay, speed, and comparator considerations, and analytical expressions are derived. Using the equation expressions, we can understand the design of comparators and make trade-offs. Based on the presented analysis, a new dynamic comparator is proposed by modifying the circuit of the conventional tail comparator for high speed and low power at small supply voltages without complicating the circuit design, resulting in a remarkable reduction in delay time and incremental speed. Simulation results in a 180 nm CMOS technology confirm the analysis results. It is shown that the proposed conventional tail comparator reduces power consumption and increases speed. The simulation results show that the proposed comparator operates up to 2.5GHz with a delay of 69ps and consumes only 329 μW at a supply voltage of 1.2 V and an offset standard deviation of 7.8 mW. Manuscript profile

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List of Articles سرعت بالا