طراحی شتاب‌دهنده تقریبی کم‌توان بر بستر تراشه‌های FPGA برای کاربردهای هوش مصنوعی

چکیده مقاله :

یکی از روش‌های یادگیری ماشین شبکه‌های عصبی می‌باشند که در کاربردهایی نظیر پردازش تصویر به کار می‌روند. یکی از چالش‌های شبکه‌های عصبی، حجم بالای محاسبات آنهاست. به همین دلیل معماری‌های زیادی برای این گونه کاربردها ارائه‌ شده که راه‌حل‌هایی برای محاسبات پیچیده آنها ارائه می‌دهند. معمولاً برای تسریع الگوریتم‌های شبکه‌های عصبی از شتاب‌دهنده‌های سخت‌افزاری قابل بازپیکربندی مانند تراشه‌های FPGA استفاده می‌شود؛ اما مشکل اصلی این تراشه‌ها توان ‌مصرفی نسبتاً بالای آنهاست. برای کاهش توان مصرفی در تراشه‌های FPGA از تکنیک محاسبات تقریبی می‌توان استفاده کرد. ایده اصلی محاسبات تقریبی این است که با ایجاد تغییراتی در مدار یا کد، بین دقت و مصرف انرژی مصالحه‌ای برقرار شود. در این پژوهش یک شبکه عصبی کانولوشنی برای تشخیص ارقام دست‌نویس به‌صورت دقیق و تقریبی با هدف بهبود توان مصرفی طراحی و پیاده‌سازی شده است. ایده تقریب‌سازی در بخش محاسبات جمع‌کننده شبکه عصبی ارائه ‌شده است. این روش با جلوگیری از انتشار رقم نقلی در بیت‌های پایین جمع‌کننده، توان مصرفی را کاهش می‌دهد. نتایج مقایسه شبکه عصبی به‌صورت دقیق و تقریبی نشان می‌دهد که با تقریب‌سازی 6 بیت وزن پایین جمع‌کننده، توان مصرفی 75_/43% کاهش می‌یابد و هیچ خطایی رخ نمی‌دهد.

چکیده انگلیسی :

One of the challenges of neural networks is the high calculations. For this reason, many architectures have been proposed for such applications, which provide solutions for their complex calculations. Reconfigurable hardware accelerators such as FPGA are usually used to accelerate neural network; But the main problem of these chips is their relatively high-power consumption. To reduce the power consumption in FPGA, the approximate calculation technique can be used. The main idea of ​​approximate computing is to make  compromise between accuracy and energy consumption by making changes in the circuit or code. In this research, a convolutional neural network has been designed and implemented to recognize handwritten digits in an accurate and approximate manner with the aim of improving the power consumption. This method reduces the power consumption by preventing the transmission of  transfer digit in the low bits of the adder. The results of the comparison of the neural network accurately and approximately show that by approximating the 6 bits of the low weight of the adder, the power consumption is reduced by 43% and no error occurs. Also, by approximating 7 bits of low weight, with 20% error, the power consumption is reduced by 44.11%

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