A low-power approximate accelerator based on FPGA chips for artificial intelligence applications
Subject Areas : electrical and computer engineeringNadia Sohrabi 1 , Amir Bavafa Toosi 2 * , Mehdi Sedighi 3
1 - Comp. Eng. Faculty, Amir Kabir University of Technology, Tehran, Iran
2 - Faculty of Com. Eng., Sadjad University, Mashhad, Iran
3 - Comp. Eng. Faculty, Amir Kabir University of Technology, Tehran, Iran
Keywords: Approximate adder, convolutional neural network, handwritten digit recognition, approximate calculations,
Abstract :
One of the challenges of neural networks is the high calculations. For this reason, many architectures have been proposed for such applications, which provide solutions for their complex calculations. Reconfigurable hardware accelerators such as FPGA are usually used to accelerate neural network; But the main problem of these chips is their relatively high-power consumption. To reduce the power consumption in FPGA, the approximate calculation technique can be used. The main idea of approximate computing is to make compromise between accuracy and energy consumption by making changes in the circuit or code. In this research, a convolutional neural network has been designed and implemented to recognize handwritten digits in an accurate and approximate manner with the aim of improving the power consumption. This method reduces the power consumption by preventing the transmission of transfer digit in the low bits of the adder. The results of the comparison of the neural network accurately and approximately show that by approximating the 6 bits of the low weight of the adder, the power consumption is reduced by 43% and no error occurs. Also, by approximating 7 bits of low weight, with 20% error, the power consumption is reduced by 44.11%
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