Design of a Phase-Locked Loop with Low Power Consumption and High Stability at 2.45 GHz

Abstract :

This paper presents the design and simulation of a phase-locked loop (PLL) with a center frequency of 2.45 GHz, implemented using 0.18 µm CMOS technology and HSPICE simulation tools. The proposed PLL architecture comprises key components including a phase detector, charge pump, low-pass filter, voltage-controlled oscillator, and frequency divider. Circuit parameters were meticulously optimized through extensive simulations to ensure high performance. Results demonstrate stable and precise operation, with a power consumption below 13.56 mW, a lock time of approximately 16 reference cycles, and a phase noise of −115 dBc/Hz at 1 MHz offset. Owing to its low power usage and robust stability, the design is well-suited for applications such as ADSL modems, Wi-Fi communication systems, and portable electronic devices.

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